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K4S640832D
CMOS SDRAM
64Mbit SDRAM
2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.0 June 1999
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 May 1999
K4S640832D
2M x 8Bit x 4 Banks Synchronous DRAM
FEATURES
* * * * JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S640832D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
* * * * *
ORDERING INFORMATION
Part No. K4S640832D-TC/L75 K4S640832D-TC/L80 K4S640832D-TC/L1H K4S640832D-TC/L1L Max Freq. 133MHz(CL=3) 125MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54 TSOP(II) Interface Package
K4S640832D-TC/L10 66MHz(CL=2 &3)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE LDQM
Data Input Register
Bank Select 2M x 8 Sense AMP 2M x 8 2M x 8 2M x 8 Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS Timing Register
Programming Register LWCBR LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 May 1999
K4S640832D
PIN CONFIGURATION (Top view)
VDD DQ0 VDDQ N.C DQ1 VSSQ N.C DQ2 VDDQ N.C DQ3 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
CMOS SDRAM
54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM DQ0 ~ 7 VDD/VSS VDDQ/VSSQ N.C/RFU
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use
Rev. 0.0 May 1999
K4S640832D
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
CMOS SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
Clock
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5 Unit pF pF pF pF Note 1 2 2 3
RAS, CAS, WE, CS, CKE, DQM Address DQ0 ~ DQ7
Notes : 1. -75 only specify a maximum value of 3.5pF 2. -75 only specify a maximum value of 3.8pF 3. -75 only specify a maximum value of 6.0pF
Rev. 0.0 May 1999
K4S640832D
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns Test Condition
CMOS SDRAM
Version - 75 - 80 - 1H - 1L -10
Unit
Note
Operating current (One bank active) Precharge standby current in power-down mode
ICC1 ICC2P
75
75
70 1 1 15
70
70
mA mA
1
ICC2PS CKE & CLK VIL(max), tCC = ICC2N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns
Precharge standby current in non power-down mode
CKE VIH(min), CLK VIL(max), tCC = ICC2NS Input signals are stable ICC3P CKE VIL(max), tCC = 10ns
mA 6 3 3 25 mA 15
Active standby current in power-down mode Active standby current in non power-down mode (One bank active)
ICC3PS CKE & CLK VIL(max), tCC = ICC3N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns
mA
CKE VIH(min), CLK VIL(max), tCC = ICC3NS Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L
Operating current (Burst mode) Refresh current Self refresh current
ICC4
115
110
95
95
95
mA
1
ICC5 ICC6
135
130 125 125 125 1 400
mA mA uA
2 3 4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S640832D-TC** 4. K4S640832D-TL** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 0.0 May 1999
K4S640832D
AC OPERATING TEST CONDITIONS(VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V
CMOS SDRAM
Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V
Unit V V ns V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol - 75 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 65 68 15 20 20 45 - 80 16 20 20 48 Version - 1H 20 20 20 50 100 70 2 2 CLK + 20 ns 1 1 1 2 1 70 80 - 1L 20 20 20 50 -10 20 24 24 50 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -80/1H/1L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported . SAMSUNG recommands tRDL=2CLK and tDAL=2CLK + 20ns.
Rev. 0.0 May 1999
K4S640832D
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CAS latency=2 CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 2.7 2.5 2.5 1.5 0.8 1 5.4 tSAC Symbol 7.5 5.4 3 3 3 2 1 1 6 - 75 Min CLK cycle time tCC Max 1000 - 80 Min 8 6 3 3 3 3 2 1 1 6 6 Max 1000 - 1H Min 10 10 6 6 3 3 3 3 2 1 1 6 7 Max 1000 - 1L Min 10 12 6 7 Max 1000
CMOS SDRAM
- 10 Min 10 13 7 7 3 3 3.5 3.5 2.5 1.5 1 7 7 ns ns ns ns ns ns 3 3 3 3 2 ns 2 ns 1,2 Max 1000 ns 1
Unit Note
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter Output rise time Output fall time Output rise time Output fall time Symbol trh tfh trh tfh Condition Measure in linear region : 1.2V ~1.8V Measure in linear region : 1.2V ~1.8V Measure in linear region : 1.2V ~1.8V Measure in linear region : 1.2V ~1.8V Min 1.37 1.30 2.8 2.0 3.9 2.9 Typ Max 4.37 3.8 5.6 5.0 Unit Volts/ns Volts/ns Volts/ns Volts/ns Notes 3 3 1,2 1,2
Notes : 1. Rise time specification based on 0pF + 50 Ohms to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 Ohms to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS.
Rev. 0.0 May 1999
K4S640832D
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
Voltage (V) 3.45 3.3 3.0 2.6 2.4 2.0 1.8 1.65 1.5 1.4 1.0 0.0 100MHz Min I (mA) 100MHz Max I (mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 66MHz Min I (mA) 0 0 -100 -200 mA -300 -400 -500 -600 Voltage 0.5 1 1.5 2
CMOS SDRAM
66MHz and 100MHz Pull-up 2.5 3 3.5
0.0 -21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0
-0.7 -7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -72.5 -93.0
IOH Min (100MHz) IOH Min (66MHz) IOH Max (66 and 100MHz)
66MHz and 100MHz Pull-down
IOL Characteristics (Pull-down)
Voltage (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 100MHz Min I (mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100MHz Max I (mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 66MHz Min I (mA) 0.0 17.7 26.9 33.3 37.6 46.6 48.0 49.5 50.7 51.5 54.2 54.9
250
200
150 mA 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5
Voltage
IOL Min (100MHz) IOL Min (66MHz) IOL Max (100MHz)
Rev. 0.0 May 1999
K4S640832D
CMOS SDRAM
Minimum V clamp current DD (Referenced to V DD) 20
VDD Clamp @ CLK, CKE,CS, DQM & DQ
VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31
15
mA
10
5
0 0 1 Voltage
I (mA)
2
3
SS Minimum V clamp current
VSS Clamp @ CLK, CKE,CS, DQM & DQ
VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 0 -10 -20 mA -30 -40 -50 -60
-3
-2
-1
0
Voltage
I (mA)
Rev. 0.0 May 1999
K4S640832D
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1
CMOS SDRAM
A10/AP A11, A9 ~ A0 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0 ~ A8) Column address (A0 ~ A8)
3 3
Bank active & row addr. Read & column address Write & Column Address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.0 May 1999

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